The present invention relates to an information handling unit, and more particularly, to an information handling unit constructed in such manner that a plurality of such information handling units may achieve information transfers therebetween through one common bus. Here, the term "information handling unit" designates generally every unit having the capabilities of transmitting program execution commands, instruction data or information data from one unit to another, or receiving them from another control system, and, more particularly, designates a processing unit, a control unit, an input/output unit, a memory unit or a combination of them, etc.
In the case where one of such information handling units achieves data transfer to or from another unit, a system comprising a plurality of information handling units has been widely employed in which data transfers are achieved by means of one common bus connecting the information handling units with each other. With regard to the procedure for utilizing the common bus in such a case, the heretofore most generally employed arrangement is as disclosed in U.S. Pat. No. 3,710,324, in which an information handling unit which wants to achieve data transfer by means of the common bus sends out a bus request signal (BR) through a bus request signal line to a bus control unit (called "processor unit" in the U.S. patent) which always supervises the state of utilization of the common bus, and in which the information handling unit was allowed to utilize the bus when it received a bus grant signal (BG) from the bus control unit, through a bus grant signal line.
In such a prior art system, however, because the bus control was performed by a single bus control unit, the system of the information handling units required two bus control lines, i.e. a bus request signal line and a bus grant signal line provided between each information handling unit and the bus control unit. This resulted in a disadvantage that the number of control lines was increased. Especially, in case where the respective information handling units are respectively formed of a monolithic integrated circuit, another disadvantage arises in that the number of external terminals of the integrated circuit is increased.
Furthermore, the bus control unit uses a timing clock to control the bus operation as a sequence of detection of bus request signals in order to select the highest priority processor and apply the bus grant signal to the highest priority processor. Therefore, the bus control needed a long processing time. This long processing time was serious in the case where a plurality of information handling units may simultaneously issue bus request signals to the bus control unit. This requires the bus control unit to select one information handling unit according to priority resulting in the processing speed of the information handling unit being unnecessarily lowered.
Still further, in the case where the aforementioned system is employed, timing must be synchronized between the respective information handling units and the bus control unit, so that a timing signal line is necessitated in addition to the two bus control lines, and an information handling unit cannot start data transfer using the bus until a timing signal is supplied thereto. This brings about another disadvantage in that the data transfer speed is further lowered.
In addition, in some cases, in order to establish priority, different circuit designs are required for the respective information handling units, and this degrades mass-producibility, imparts unnecessary limitations to information handling units which can be practically equipped, and thus lowers a versatility of the information handling units.